Timing Slack Calculator

This free timing slack calculator checks a register-to-register path in an FPGA or ASIC design. Enter the clock frequency, flip-flop clock-to-Q, setup and hold times, data path delay, clock skew and uncertainty to get the setup slack, hold slack, maximum clock frequency (Fmax) and the logic delay budget — the same quantities static timing analysis tools like Vivado, Quartus and PrimeTime report.

Setup and hold slack formulas

Setup slack = (T_clk + skew − uncertainty) − (T_cq + D_max + T_su)
Hold slack = (T_cq + D_min) − (T_h + skew + uncertainty)
Fmax = 1 ÷ (T_cq + D_max + T_su − skew + uncertainty)

Worked example

At 200 MHz the period is 5 ns. With T_cq = 0.3 ns, a 3.5 ns data path, T_su = 0.1 ns and 0.1 ns of uncertainty, the data needs 3.9 ns and has 4.9 ns available: setup slack = +1.0 ns. The path could run at up to 1 ÷ 4.0 ns = 250 MHz. With a 0.5 ns shortest path and 0.05 ns hold time, hold slack = +0.65 ns.

Clock period and logic budget by frequency

Time left for logic and routing between two registers, assuming T_cq = 0.3 ns, T_su = 0.1 ns, 0.1 ns uncertainty and no skew. Real figures depend on the device and speed grade.

Clock	Period	Logic + routing budget
50 MHz	20 ns	19.5 ns
100 MHz	10 ns	9.5 ns
125 MHz	8 ns	7.5 ns
150 MHz	6.667 ns	6.17 ns
200 MHz	5 ns	4.5 ns
250 MHz	4 ns	3.5 ns
300 MHz	3.333 ns	2.83 ns
400 MHz	2.5 ns	2 ns
500 MHz	2 ns	1.5 ns

Related calculations

Generate the clock with the FPGA clock divider and PLL calculator.
Size the buffer between two clock domains with the FIFO depth calculator.

Frequently asked questions

What is timing slack?

Slack is the margin by which a path meets its timing requirement. For setup, it is the time the data arrives before it is required at the capturing flip-flop; for hold, it is how long the data stays stable after the clock edge beyond the hold requirement. Positive slack passes, negative slack is a timing violation.

How do I calculate setup slack?

Setup slack = (clock period + clock skew − clock uncertainty) − (clock-to-Q + data path delay + setup time). For a 200 MHz clock (5 ns), 0.3 ns clock-to-Q, 3.5 ns of logic and routing, 0.1 ns setup and 0.1 ns uncertainty with no skew: 5 − 0.1 − (0.3 + 3.5 + 0.1) = 1.0 ns of slack.

How do I calculate hold slack?

Hold slack = (clock-to-Q + minimum data path delay) − (hold time + clock skew + uncertainty). Hold does not depend on the clock period, so slowing the clock never fixes a hold violation. Tools fix hold by adding delay to the short path.

How do I fix negative setup slack?

Reduce the logic between registers (pipelining, retiming, or simpler logic with fewer levels), improve placement so routing is shorter, use faster resources such as DSP or carry chains, reduce fan-out by duplicating registers, or lower the clock frequency. In FPGAs, routing often accounts for half or more of the path delay.

Does clock skew help or hurt timing?

Positive skew — the capture clock arriving later than the launch clock — gives setup more time but makes hold harder. Negative skew does the opposite. That is why skew is added to the setup requirement and subtracted from the hold margin in the formulas.

What are WNS and TNS?

Worst negative slack (WNS) is the slack of the single worst path; if it is zero or positive, the design meets timing. Total negative slack (TNS) is the sum of the negative slack of all failing endpoints, which shows how widespread the problem is. Vivado, Quartus and other tools report both.