This free number base converter translates between binary, decimal, hexadecimal and octal — binary to decimal, decimal to hex, hex to binary and back — at 8, 16, 32 or 64 bits. It is also a two's complement calculator: switch between signed and unsigned to see how the same bit pattern reads either way. Ready-to-paste Verilog, VHDL and C literals are generated for every value.
How to use the converter
Type in any field and the others update. Hex, binary and octal are treated as raw bit patterns at the chosen width; the
decimal field shows that pattern as a signed (two's complement) or unsigned number. Prefixes like 0x and
0b, spaces and underscores are ignored, so you can paste values straight from code or a waveform viewer.
Hex, binary and decimal chart (0–15)
Each hex digit is exactly four binary bits, so longer values convert one digit at a time.
| Decimal | Hex | Binary | Octal |
|---|---|---|---|
| 0 | 0 | 0000 | 0 |
| 1 | 1 | 0001 | 1 |
| 2 | 2 | 0010 | 2 |
| 3 | 3 | 0011 | 3 |
| 4 | 4 | 0100 | 4 |
| 5 | 5 | 0101 | 5 |
| 6 | 6 | 0110 | 6 |
| 7 | 7 | 0111 | 7 |
| 8 | 8 | 1000 | 10 |
| 9 | 9 | 1001 | 11 |
| 10 | A | 1010 | 12 |
| 11 | B | 1011 | 13 |
| 12 | C | 1100 | 14 |
| 13 | D | 1101 | 15 |
| 14 | E | 1110 | 16 |
| 15 | F | 1111 | 17 |
Integer ranges by bit width
| Width | Unsigned range | Signed (two's complement) range |
|---|---|---|
| 8-bit | 0 to 255 | -128 to 127 |
| 16-bit | 0 to 65,535 | -32,768 to 32,767 |
| 32-bit | 0 to 4,294,967,295 | -2,147,483,648 to 2,147,483,647 |
| 64-bit | 0 to 18,446,744,073,709,551,615 | -9,223,372,036,854,775,808 to 9,223,372,036,854,775,807 |
Two's complement explained
To find the two's complement representation of a negative number:
- Write the positive value in binary: 1234 = 0000 0100 1101 0010 (16-bit).
- Invert every bit: 1111 1011 0010 1101.
- Add 1: 1111 1011 0010 1110 = 0xFB2E, which is −1234.
Reading it back, a set MSB means the value is negative: subtract 2ᴺ from the unsigned value. 0xFB2E = 64,302 unsigned, and 64,302 − 65,536 = −1234.
Sign extension
When widening a signed value, copy the MSB into the new upper bits: 8-bit 0xF6 (−10) becomes 16-bit 0xFFF6. Zero-extending
it instead (0x00F6) turns it into +246 — a classic RTL bug. In Verilog, declare both operands signed or use
$signed() so the tools sign-extend for you.