FIFO Depth Calculator

This free FIFO depth calculator finds the minimum depth of a FIFO buffer that absorbs a burst of writes when the write and read sides run at different clock frequencies — with or without idle cycles between writes and reads. It gives the exact minimum and the next power of two for an asynchronous (dual-clock) FIFO, and checks that the reader keeps up over the long term. It is the classic RTL and ASIC/FPGA design interview question, solved step by step.

FIFO depth formula

Write rate = f_write ÷ (write every N clocks) · Read rate = f_read ÷ (read every M clocks)
Burst time = burst length ÷ write rate
Words read during burst = ⌊burst time × read rate⌋
Minimum depth = burst length − words read during burst

Worked example

A 120-word burst written every cycle at 100 MHz takes 1.2 µs. A 50 MHz reader removes 60 words in that time, so the FIFO must hold 120 − 60 = 60 words. An asynchronous FIFO would use the next power of two: 64.

FIFO depth for common scenarios

Write	Read	Burst	Minimum depth	Async (2ⁿ)
100 MHz	50 MHz	120 words	60	64
80 MHz	50 MHz	120 words	45	64
100 MHz	100 MHz, 1 in 2	120 words	60	64
200 MHz	100 MHz	256 words	128	128
100 MHz	80 MHz	120 words	24	32
125 MHz	100 MHz	1,500 words	300	512

Design notes

The reader must keep up on average. A FIFO only absorbs bursts; if data arrives faster than it leaves over the long run, any depth eventually overflows.
Use almost-full flags with a threshold that leaves room for the writes already in flight when back-pressure is applied.
Async FIFOs need Gray-coded pointers, 2–3 stage synchronizers and a power-of-two depth. Most FPGA vendors provide a verified FIFO generator.
Need the clock ratios first? Use the FPGA clock divider and PLL calculator, then check timing with the timing slack calculator.

Frequently asked questions

How do I calculate FIFO depth?

Work out how long the write burst takes, how many words the reader removes in that time, and subtract: depth = burst length − (burst time × read rate). For example, writing 120 words at 100 MHz takes 1.2 µs; a 50 MHz reader removes 60 words in that time, so the FIFO must hold the other 60.

FIFO depth with idle cycles: a worked interview example

Write clock 80 MHz with one write every 2 cycles, read clock 50 MHz with one read every 3 cycles, burst of 120 words. Write rate = 40 Mwords/s, so the burst takes 3 µs. Read rate = 16.7 Mwords/s, so 50 words are read during the burst. Minimum depth = 120 − 50 = 70 words.

Why should an asynchronous FIFO depth be a power of two?

Async FIFOs pass their read and write pointers across clock domains as Gray code, where only one bit changes per step. A Gray-code sequence only wraps cleanly — still changing one bit — when the depth is a power of two. Non-power-of-two async FIFOs are possible but need special pointer encoding.

What if the read side is faster than the write side?

Then data never accumulates during a burst and only a small FIFO is needed — enough to absorb the clock-domain-crossing latency, typically 8–16 words for an async FIFO. The calculator still reports at least 1 word.

Does this account for synchronizer latency?

Not directly. In an async FIFO the full and empty flags are updated a few clocks late because the pointers pass through 2–3 flip-flop synchronizers. Add a few words of margin on top of the minimum, which rounding up to the next power of two usually covers.