FPGA Clock Divider & PLL Calculator

This free FPGA clock calculator does two jobs. For a simple clock divider it gives the divide ratio, the counter width, the exact output frequency and error, and ready-to-paste Verilog for a clock-enable counter. For a PLL or MMCM it searches every valid multiply (M), input divide (D) and output divide (O) combination within the VCO and phase detector limits and lists the closest settings to your target frequency — handy for VGA, HDMI, Ethernet and memory clocks on Xilinx, AMD, Intel and Lattice FPGAs.

Clock divider and PLL formulas

Divider: N = round(Fin ÷ Ftarget) · Fout = Fin ÷ N · counter bits = ⌈log₂ N⌉
PLL / MMCM: Fpfd = Fin ÷ D · Fvco = Fin × M ÷ D · Fout = Fvco ÷ O
Error (ppm) = (Fout − Ftarget) ÷ Ftarget × 10⁶

Worked example

For 25.175 MHz from a 100 MHz board clock on a 7-series MMCM, the best integer setting is M = 34, D = 3, O = 45: VCO = 100 × 34 ÷ 3 = 1,133.333 MHz, and 1,133.333 ÷ 45 = 25.1852 MHz, an error of 405 ppm.

PLL settings for common clocks (100 MHz input, 7-series MMCM)

Use	Target MHz	M	D	O	Fout MHz	Error ppm
VGA 640×480 @ 60 Hz	25.175	34	3	45	25.1852	405
SVGA 800×600 @ 60 Hz	40	12	1	30	40	0
720p / 1080i video	74.25	49	6	11	74.2424	-102
1080p @ 60 Hz	148.5	52	5	7	148.5714	481
DDR3 / memory interface	200	12	1	6	200	0
Gigabit Ethernet GMII	125	45	4	9	125	0

Limits are typical Xilinx 7-series values for the -1 speed grade (MMCM VCO 600–1200 MHz). Other families and speed grades differ — check the datasheet, choose Custom limits, and confirm the result in the vendor clocking wizard. The MMCM also supports fractional M and O values in 1/8 steps, which this integer search does not use.

Related calculations

Check whether your logic meets timing at the new clock with the timing slack calculator.
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Frequently asked questions

How do I calculate the PLL output frequency?

For a Xilinx MMCM or PLL, Fout = Fin × M ÷ (D × O): the input is divided by D to the phase detector frequency, multiplied by M up to the VCO frequency, then divided by O at the output. The VCO and phase detector frequencies must stay inside the ranges in the device datasheet. Intel/Altera PLLs use the same idea with N, M and C counters.

What PLL settings give 25.175 MHz from 100 MHz?

With integer settings on a 7-series MMCM, M = 34, D = 3, O = 45 gives a VCO of 1,133.333 MHz and an output of 25.1852 MHz (405 ppm). Most monitors tolerate small pixel-clock errors, which is why many FPGA projects simply drive 640×480 at 25.0 MHz.

Can an FPGA generate exactly 148.5 MHz from 100 MHz?

Not exactly with integer settings: the closest 7-series MMCM setting is M = 52, D = 5, O = 7, giving 148.5714 MHz (481 ppm). Use the MMCM's fractional divider (0.125 steps), cascade two MMCMs, or use a 148.5 MHz / 27 MHz oscillator for exact video timing.

Should I divide a clock with a counter or use a clock enable?

In an FPGA, avoid using a counter output as a clock: it is routed on general fabric, adds skew and makes timing analysis hard. Instead, keep everything on the fast clock and generate a one-cycle clock-enable pulse every N cycles. Use a PLL or MMCM when you genuinely need a new clock, for example to drive an external interface.

Why prefer a higher VCO frequency?

For the same output, a higher VCO frequency generally gives lower output jitter, and a higher phase detector frequency (smaller D) tracks the input better. That is why the calculator ranks solutions with equal error by VCO frequency. Always confirm the final settings in the vendor clocking wizard.

Clock divider / clock enable

PLL / MMCM settings

Clock divider and PLL formulas

Worked example

PLL settings for common clocks (100 MHz input, 7-series MMCM)

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Frequently asked questions

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